Self-tuning the parallelism degree in Parallel-Nested Software Transactional Memory

Transactional Memory is a promising parallel computing paradigm, increasingly used nowadays, that allows easy parallelization of sequential programs and can expose a great level of parallelism. Many different approaches exist. One such approach is parallel-nested Transactional Memory, where transactions are allowed to spawn their own child transactions, effectively exposing additional levels of fine-grained parallelism. Transactional Memory systems often have tuning mechanisms, which adjust parameters and internal dynamics according to system measurements, to increase performance. To the best of our knowledge, tuning nested Transactional Memory systems has not been explored in contemporary research. We propose to create a tuning mechanism for parallel-nested Transactional Memory, and perform an analysis using a state of the art Transactional Memory system, JVSTM. We develop mechanisms to plug different tuning strategies into JVSTM, and evaluate their effects and improvements, or lack thereof, using a set of benchmarks designed for evaluating STM systems. The results we obtained offer insights on the different tuning strategies, as well as a framework with which future work can be developed.